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MT41K64M16TW-107:J
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.
Packaging: TRY
Supplier Type: Authorized Distributor | 2,853
available | | | Qty | Price |
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| 1 | 3.8657 | | 10 | 3.7591 | | 30 | 3.6524 | | 50 | 3.5724 | | 100 | 3.4658 | | 250 | 3.3592 | | 500 | 3.2525 |
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FM24C04B-GTR
Category: FRAM, Memory & Storage › Memory ICsInfineon |
Infineon | The FM24C04B is a 4-Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by EEPROM and other nonvolatile memories. Unlike EEPROM, the FM24C04B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. The FM24C04B is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM. These capabilities make the FM24C04B ideal for nonvolatile memory applications, requiring frequent or rapid writes. Examples range from data logging, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system.
Packaging: TR
Supplier Type: Authorized Distributor | 5,000
available | | | Qty | Price |
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| 695 | 1.5178 | | 700 | 1.4731 | | 1,400 | 1.4285 | | 3,500 | 1.3838 | | 7,000 | 1.3392 | | 35,000 | 1.2946 | | 70,000 | 1.2499 |
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CY62126EV30LL-45ZSXIT
Category: Memory & Storage › Memory ICs › SRAMInfineon |
Infineon | SRAM Chip Async Single 3V 1M-bit 64K x 16 45ns 44-Pin TSOP-II T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 1,000
available | | | Qty | Price |
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| 8 | 5.4544 | | 10 | 4.6323 | | 50 | 3.5256 | | 100 | 3.5098 | | 200 | 3.3044 | | 500 | 2.909 | | 1,000 | 2.8299 |
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