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MT25QL128ABA8ESF-0SIT
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | MT25QL128ABA8ESF-0SIT is a 3V, multiple I/O, sector erase, serial NOR flash memory. It is a high-performance multiple input/output serial flash memory device. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual, and quad input/output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Packaging: TRY
Supplier Type: Authorized Distributor | 3,454
available | | | Qty | Price |
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| 1 | 3.4522 | | 10 | 3.3569 | | 30 | 3.2617 | | 50 | 3.1903 | | 100 | 3.095 | | 250 | 2.9998 | | 500 | 2.9046 |
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KSZ8795CLXIC
Category: Computing › Computing & Storage › Ethernet Switch, Memory & StorageMicrochip |
Microchip | The KSZ8795 is a highly-integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and RMII modes. The KSZ8795CLX product is built upon Microchip's industry-leading Ethernet latest analog and digital technology, with features designed to offload host processing and streamline your overall design. - Four integrated 10/100Base-T/TX MAC/PHYs - One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces - Small 80-pin LQFP package.
Packaging: BLK
Supplier Type: Authorized Distributor | 700
available | | | Qty | Price |
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| 1 | 9.0396 | | 10 | 8.2832 | | 25 | 7.5268 | | 50 | 7.4028 | | 100 | 7.2788 |
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MT41K64M16TW-107:J
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.
Packaging: TRY
Supplier Type: Authorized Distributor | 2,853
available | | | Qty | Price |
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| 1 | 3.8657 | | 10 | 3.7591 | | 30 | 3.6524 | | 50 | 3.5724 | | 100 | 3.4658 | | 250 | 3.3592 | | 500 | 3.2525 |
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