MT47H128M8SH-25E IT:M
Category: DRAM , Memory & Storage › Memory ICs Micron
Micron The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. Packaging: TRYSupplier Type: Authorized Distributor1,857 Qty Price 1 5.6889 10 5.53196 30 5.37502 50 5.25728 100 5.10034 250 4.9434 500 4.78646
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S25FS512SAGMFI011
Category: Flash Memory , Memory & Storage › Memory ICs Infineon
Infineon NOR Flash Serial (SPI, Dual SPI, Quad SPI) 1.8V 512M-bit 512M/256M/128M x 1/2-bit/4-bit 8ns 16-Pin SOIC W Tube Packaging: N/ASupplier Type: Authorized Distributor705 Qty Price 4 17.5966 10 14.98476 50 14.36484 100 13.39114 200 12.81546 500 12.59412
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MT47H128M16RT-25E AIT:C TR
Category: DRAM , Memory & Storage › Memory ICs Micron
Micron N/APackaging: TRSupplier Type: Authorized Distributor 1,000 Qty Price 1,000 21.93954 2,000 21.63056 4,000 21.0126 6,000 20.54906 8,000 19.77654 10,000 19.46756 100,000 19.15844
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