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FM24C04B-GTR
Category: FRAM, Memory & Storage › Memory ICsInfineon |
Infineon | The FM24C04B is a 4-Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by EEPROM and other nonvolatile memories. Unlike EEPROM, the FM24C04B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. The FM24C04B is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM. These capabilities make the FM24C04B ideal for nonvolatile memory applications, requiring frequent or rapid writes. Examples range from data logging, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system.
Packaging: TR
Supplier Type: Authorized Distributor | 5,000
available | | | Qty | Price |
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| 695 | 1.5178 | | 700 | 1.4731 | | 1,400 | 1.4285 | | 3,500 | 1.3838 | | 7,000 | 1.3392 | | 35,000 | 1.2946 | | 70,000 | 1.2499 |
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MT47H128M8SH-25E IT:M
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.
Packaging: TRY
Supplier Type: Authorized Distributor | 1,857
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| 1 | 4.0635 | | 10 | 3.9514 | | 30 | 3.8393 | | 50 | 3.7552 | | 100 | 3.6431 | | 250 | 3.531 | | 500 | 3.4189 |
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93LC86CT-I/SN
Category: EEPROM, Memory & Storage › Memory ICsMicrochip |
Microchip | EEPROM Serial-Microwire 16K-bit 2K x 8/1K x 16 3.3V/5V 8-Pin SOIC N T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 3,300
available | | |
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