KSZ8795CLXIC
Category: Computing › Computing & Storage › Ethernet Switch , Memory & Storage Microchip
Microchip The KSZ8795 is a highly-integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and RMII modes. The KSZ8795CLX product is built upon Microchip's industry-leading Ethernet latest analog and digital technology, with features designed to offload host processing and streamline your overall design. - Four integrated 10/100Base-T/TX MAC/PHYs - One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces - Small 80-pin LQFP package. Packaging: BLKSupplier Type: Authorized Distributor700 Qty Price 1 12.65544 10 11.59648 25 10.53752 50 10.36392 100 10.19032
Add to cart
This product is already in your quote request list.
MT47H128M8SH-25E IT:M
Category: DRAM , Memory & Storage › Memory ICs Micron
Micron The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. Packaging: TRYSupplier Type: Authorized Distributor1,857 Qty Price 1 5.6889 10 5.53196 30 5.37502 50 5.25728 100 5.10034 250 4.9434 500 4.78646
Add to cart
This product is already in your quote request list.
M24C08-WMN6TP
Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics
STMicroelectronics EEPROM Serial-I2C 8K-bit 1K x 8 3.3V/5V 8-Pin SO N T/R Packaging: N/ASupplier Type: Authorized Distributor75,000 Qty Price 7,500 0.21056 10,000 0.20202 15,000 0.19992 25,000 0.1981
Add to cart
This product is already in your quote request list.
