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TMS5704357BZWTQQ1
Category: MCUsTexas Instruments |
Texas Instruments | MCU 32-bit ARM Cortex R5F RISC 4MB Flash 1.2V/3.3V 337-Pin NFBGA Tray Automotive AEC-Q100
Packaging: N/A
Supplier Type: Authorized Distributor | 90
available | | | Qty | Price |
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| 1 | 69.5516 | | 10 | 64.7528 | | 25 | 57.5732 |
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STM32F479NIH6
Category: MCUsSTMicroelectronics |
STMicroelectronics | MCU 32-bit ARM Cortex M4 RISC 2MB Flash 1.8V/2.5V/3.3V Medical 216-Pin TFBGA Tray
Packaging: N/A
Supplier Type: Authorized Distributor | 165
available | | | Qty | Price |
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| 1 | 24.9364 | | 10 | 22.816 | | 25 | 19.8524 | | 160 | 19.1952 | | 320 | 18.5752 | | 480 | 17.0376 |
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MCF5282CVM66
Category: 32 Bit Microcontrollers, MCUsNXP |
NXP | 32 Bit Microcontroller, Coldfire V2 Family MCF528x Series Microcontrollers, ColdFire v2, 32 bit The MCF5282CVM66 is a 32-bit Microcontroller based on the ColdFire V2 core and integrated with Ethernet, CAN and flash. These devices offer advanced communications features, a rich peripheral set and a variety of supporting software and development tools. With its integrated 10/100 Mbps Ethernet MAC and network-ready applications software. The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.
Packaging: TRY
Supplier Type: Authorized Distributor | 152
available | | | Qty | Price |
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| 1 | 64.736172 | | 2 | 63.660924 | | 4 | 62.5773 | | 8 | 61.494948 | | 16 | 60.95394 |
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