MT47H128M16RT-25E AIT:C TR
Category: DRAMs Micron
Micron N/APackaging: TRSupplier Type: Authorized Distributor 1,000 Qty Price 1,000 15.6711 2,000 15.4504 4,000 15.009 6,000 14.6779 8,000 14.1261 10,000 13.9054 100,000 13.6846
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MT47H128M16RT-25E AIT:C
Category: DRAMs Micron
Micron N/APackaging: TRYSupplier Type: Authorized Distributor 1,260 Qty Price 1,260 15.6711 1,300 15.4504 2,600 15.009 6,300 14.6779 13,000 14.1261 63,000 13.9054 130,000 13.6846
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1032921
Category: Contactors , Solid State Phoenix Contact
Phoenix Contact Contactors - Solid State Solid State Contact 24V DC Packaging: N/ASupplier Type: Authorized Distributor36
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MT41K64M16TW-107:J
Category: DRAM Chip , DRAMs Micron
Micron DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Packaging: TRYSupplier Type: Authorized Distributor2,853 Qty Price 1 3.8657 10 3.7591 30 3.6524 50 3.5724 100 3.4658 250 3.3592 500 3.2525
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AS4C256M16D3C-12BCN
Category: DRAMs Alliance Memory
Alliance Memory DRAM, DDR3, 4 Gbit, 256M x 16bit, 800 MHz, FBGA, 96 Pins AS4C256M16D3C-12BCN is a 256M x 16bit DDR3 synchronous DRAM (SDRAM). The 4Gb double-data-rate-3 DRAM is a double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 4Gb chip is organized as 32Mbit x 16I/Os x 8 bank devices. This synchronous device achieves high-speed double-data-rate transfer rates of up to 2133Mb/sec/pin for general applications. The chip is designed to comply with all DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source-synchronous fashion. Packaging: TRYSupplier Type: Authorized Distributor942 Qty Price 1 11.9196 10 11.008564 30 10.131576 50 10.03275 100 9.9813
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MT47H128M8SH-25E IT:M
Category: DRAM Chip , DRAMs Micron
Micron The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. Packaging: TRYSupplier Type: Authorized Distributor1,857 Qty Price 1 4.0635 10 3.9514 30 3.8393 50 3.7552 100 3.6431 250 3.531 500 3.4189
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MT47H128M16RT-25EIT:C
Category: DRAMs Micron
Micron N/APackaging: TRYSupplier Type: Authorized Distributor 1,440 Qty Price 1 14.5458 10 14.1446 30 13.7433 50 13.4423 100 13.0411 250 12.6398 500 12.2386
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UPD720210K8-BAF-A
Category: No Category , USB / Flash / Pen Drives Renesas Electronics
Renesas Electronics N/APackaging: TRYSupplier Type: Authorized Distributor 165
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D2516EC4BXGJD-U
Category: DRAMs Kingston Technology
Kingston Technology N/A Packaging: BLKSupplier Type: Authorized Distributor7,870 Qty Price 1 Contact ASC For Pricing
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