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S29GL512P10TFIR10
Category: Flash Memory, Memory & Storage › Memory ICsInfineon |
Infineon | NOR Flash Parallel 3.3V 512M-bit 64M x 8/32M x 16 100ns 56-Pin TSOP Tray
Packaging: N/A
Supplier Type: Authorized Distributor | 2
available | | | Qty | Price |
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| 1 | 8.65046 | | 10 | 8.12532 | | 25 | 7.6902 | | 50 | 7.35476 | | 100 | 7.15904 | | 500 | 6.91558 |
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M24C16-WMN6TP
Category: EEPROM, Memory & Storage › Memory ICsSTMicroelectronics |
STMicroelectronics | EEPROM, I2C, 16 Kbit, 2K x 8bit, 400 kHz, 8 Pins, NSOIC The devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as as 2048x8 bits, 1024x8 bits, 512x8 bits, 256x8 bits (M24C16, M24C08, M24C04 and M24C02).The devices are compatible with all I²C modes up to 400 kHz and can operate with a s
Packaging: TR
Supplier Type: Authorized Distributor | 75,000
available | | |
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M24C32-WMN6P
Category: EEPROM, Memory & Storage › Memory ICsSTMicroelectronics |
STMicroelectronics | The M24C32 is a 32-Kbit I²C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 4 K × 8 bits.This I²C EEPROM can operate with a supply voltage from 2.5 V up to 5.5 V over an ambient temperature range of -40 °C / 125 °C.The device is compliant with the Automotive standard AEC-Q100 grade 1.
Packaging: BLK
Supplier Type: Authorized Distributor | 6,739
available | | | Qty | Price |
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| 1 | 0.5208 | | 10 | 0.50862 | | 100 | 0.41496 | | 500 | 0.40446 | | 1,000 | 0.39228 |
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M24C32-WMN6TP
Category: EEPROM, Memory & Storage › Memory ICsSTMicroelectronics |
STMicroelectronics | EEPROM, I2C, Serial, 32 Kbit, 4K x 8bit, 1 MHz, 8 Pins, SOIC N M24C32-WMN6TP is a 32Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 4K x 8 bits.
Packaging: TR
Supplier Type: Authorized Distributor | 90,499
available | | |
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M24C08-WMN6TP
Category: EEPROM, Memory & Storage › Memory ICsSTMicroelectronics |
STMicroelectronics | EEPROM Serial-I2C 8K-bit 1K x 8 3.3V/5V 8-Pin SO N T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 75,000
available | | | Qty | Price |
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| 7,500 | 0.21056 | | 10,000 | 0.20202 | | 15,000 | 0.19992 | | 25,000 | 0.1981 |
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M24C08-WMN6P
Category: EEPROM, Memory & Storage › Memory ICsSTMicroelectronics |
STMicroelectronics | EEPROM, I2C, Serial, 8 Kbit, 1K x 8bit, 400 kHz, 8 Pins, SOIC N The devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as as 2048x8 bits, 1024x8 bits, 512x8 bits, 256x8 bits (M24C16, M24C08, M24C04 and M24C02).The devices are compatible with all I²C modes up to 400 kHz and can operate with a s
Packaging: RAL
Supplier Type: Authorized Distributor | 28,000
available | | |
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ATSHA204A-STUCZ-T
Category: EEPROM, Memory & Storage › Memory ICsMicrochip |
Microchip | The Microchip ATSHA204A is a full turnkey security device. It includes a 4.5Kb EEPROM divided into 16 slots. This array can be used for storage of keys, miscellaneous read/write, read-only, password or secret data, and consumption tracking. Access to the various sections of memory can be restricted in a variety of ways and then the configuration locked to prevent changes.Access to the chip is through a standard I²C interface at speeds up to 1Mb/sec. The chip also supports a single-wire interface that can reduce the number of GPIOs required on the system processor and/or reduce the number of pins on connectors. It is compatible with most UART or serial I/O controllers. System integration is eased with a wide supply voltage range and an ultra-low sleep current of less than 100nA.
Packaging: TAP
Supplier Type: Authorized Distributor | 4,481
available | | | Qty | Price |
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| 1 | 1.2222 | | 25 | 1.09718 | | 50 | 1.07982 | | 100 | 1.06246 |
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24AA01T-I/OT
Category: EEPROM, Memory & Storage › Memory ICsMicrochip |
Microchip | The Microchip Technology Inc. 24AA01/24LC01B is a 1Kb Serial EEPROM. The device is organized as one block of 128 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V with standby and active currents of only 1 µA and 1 mA, respectively. The 24XX01 also has a page write capability for up to 8 bytes of data. The 24XX01 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN and MSOP packages, and is also available in the 5-lead SOT-23 package.
Packaging: TR
Supplier Type: Authorized Distributor | 114,000
available | | |
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MT41K64M16TW-107:J
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.
Packaging: TRY
Supplier Type: Authorized Distributor | 2,853
available | | | Qty | Price |
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| 1 | 5.41198 | | 10 | 5.26274 | | 30 | 5.11336 | | 50 | 5.00136 | | 100 | 4.85212 | | 250 | 4.70288 | | 500 | 4.5535 |
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MT41K64M16TW-107:J TR
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | DRAM Chip DDR3 SDRAM 1Gbit 64Mx16 1.35V 96-Pin FBGA T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 2,000
available | | |
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MT25QL128ABA8ESF-0SIT
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | MT25QL128ABA8ESF-0SIT is a 3V, multiple I/O, sector erase, serial NOR flash memory. It is a high-performance multiple input/output serial flash memory device. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual, and quad input/output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Packaging: TRY
Supplier Type: Authorized Distributor | 3,454
available | | | Qty | Price |
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| 1 | 4.83308 | | 10 | 4.69966 | | 30 | 4.56638 | | 50 | 4.46642 | | 100 | 4.333 | | 250 | 4.19972 | | 500 | 4.06644 |
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MT25QL128ABA8ESF-0SIT TR
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | NOR Flash Serial (SPI, Dual SPI, Quad SPI) 3V/3.3V 128M-bit 128M/64M/32M x 1/2-bit/4-bit 6ns 16-Pin SOP-II T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 5
available | | |
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MT47H128M8SH-25E IT:M
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.
Packaging: TRY
Supplier Type: Authorized Distributor | 1,857
available | | | Qty | Price |
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| 1 | 5.6889 | | 10 | 5.53196 | | 30 | 5.37502 | | 50 | 5.25728 | | 100 | 5.10034 | | 250 | 4.9434 | | 500 | 4.78646 |
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MT25QL128ABA1ESE-0SIT
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | The MT25Q is a high-performance multiple input/output serial Flash memory device manufactured on 45nm NOR technology. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual and quad input/ output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Packaging: BLK
Supplier Type: Authorized Distributor | 1,473
available | | | Qty | Price |
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| 1 | 6.73568 | | 10 | 5.642 | | 25 | 5.58992 | | 50 | 5.52048 | | 100 | 5.4684 |
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MT25QL128ABA1ESE-0SIT TR
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | NOR Flash Serial (SPI, Dual SPI, Quad SPI) 3V/3.3V 128M-bit 128M/64M/32M x 1/2-bit/4-bit 6ns 8-Pin SOIC W T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 12,000
available | | |
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MT47H128M16RT-25EIT:C
Category: DRAMMicron |
Micron | N/A
Packaging: TRY
Supplier Type: Authorized Distributor | 1,440
available | | | Qty | Price |
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| 1 | 20.36412 | | 10 | 19.80244 | | 30 | 19.24062 | | 50 | 18.81922 | | 100 | 18.25754 | | 250 | 17.69572 | | 500 | 17.13404 |
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MT47H128M16RT-25E AIT:C TR
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | N/A
Packaging: TR
Supplier Type: Authorized Distributor | 1,000
available | | | Qty | Price |
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| 1,000 | 21.93954 | | 2,000 | 21.63056 | | 4,000 | 21.0126 | | 6,000 | 20.54906 | | 8,000 | 19.77654 | | 10,000 | 19.46756 | | 100,000 | 19.15844 |
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MT47H128M16RT-25E AIT:C
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | N/A
Packaging: TRY
Supplier Type: Authorized Distributor | 1,260
available | | | Qty | Price |
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| 1,260 | 21.93954 | | 1,300 | 21.63056 | | 2,600 | 21.0126 | | 6,300 | 20.54906 | | 13,000 | 19.77654 | | 63,000 | 19.46756 | | 130,000 | 19.15844 |
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93LC86CT-I/SN
Category: EEPROM, Memory & Storage › Memory ICsMicrochip |
Microchip | EEPROM Serial-Microwire 16K-bit 2K x 8/1K x 16 3.3V/5V 8-Pin SOIC N T/R
Packaging: N/A
Supplier Type: Authorized Distributor | 3,300
available | | |
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S25FS512SAGMFI011
Category: Flash Memory, Memory & Storage › Memory ICsInfineon |
Infineon | NOR Flash Serial (SPI, Dual SPI, Quad SPI) 1.8V 512M-bit 512M/256M/128M x 1/2-bit/4-bit 8ns 16-Pin SOIC W Tube
Packaging: N/A
Supplier Type: Authorized Distributor | 705
available | | | Qty | Price |
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| 4 | 17.5966 | | 10 | 14.98476 | | 50 | 14.36484 | | 100 | 13.39114 | | 200 | 12.81546 | | 500 | 12.59412 |
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