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MT25QL128ABA8ESF-0SIT
Category: Flash Memory, Memory & Storage › Memory ICsMicron |
Micron | MT25QL128ABA8ESF-0SIT is a 3V, multiple I/O, sector erase, serial NOR flash memory. It is a high-performance multiple input/output serial flash memory device. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual, and quad input/output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Packaging: TRY
Supplier Type: Authorized Distributor | 3,454
available | | | Qty | Price |
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| 1 | 3.4522 | | 10 | 3.3569 | | 30 | 3.2617 | | 50 | 3.1903 | | 100 | 3.095 | | 250 | 2.9998 | | 500 | 2.9046 |
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MT47H128M8SH-25E IT:M
Category: DRAM, Memory & Storage › Memory ICsMicron |
Micron | The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.
Packaging: TRY
Supplier Type: Authorized Distributor | 1,857
available | | | Qty | Price |
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| 1 | 4.0635 | | 10 | 3.9514 | | 30 | 3.8393 | | 50 | 3.7552 | | 100 | 3.6431 | | 250 | 3.531 | | 500 | 3.4189 |
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ATSHA204A-STUCZ-T
Category: EEPROM, Memory & Storage › Memory ICsMicrochip |
Microchip | The Microchip ATSHA204A is a full turnkey security device. It includes a 4.5Kb EEPROM divided into 16 slots. This array can be used for storage of keys, miscellaneous read/write, read-only, password or secret data, and consumption tracking. Access to the various sections of memory can be restricted in a variety of ways and then the configuration locked to prevent changes.Access to the chip is through a standard I²C interface at speeds up to 1Mb/sec. The chip also supports a single-wire interface that can reduce the number of GPIOs required on the system processor and/or reduce the number of pins on connectors. It is compatible with most UART or serial I/O controllers. System integration is eased with a wide supply voltage range and an ultra-low sleep current of less than 100nA.
Packaging: TAP
Supplier Type: Authorized Distributor | 4,481
available | | | Qty | Price |
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| 1 | 0.873 | | 25 | 0.7837 | | 50 | 0.7713 | | 100 | 0.7589 |
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