S29GL512P10TFIR10 Category: Flash Memory , Memory & Storage › Memory ICs Infineon Infineon NOR Flash Parallel 3.3V 512M-bit 64M x 8/32M x 16 100ns 56-Pin TSOP Tray Packaging: N/ASupplier Type: Authorized Distributor2 Qty Price 1 6.1789 10 5.8038 25 5.493 50 5.2534 100 5.1136 500 4.9397
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M24C16-WMN6TP Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics STMicroelectronics EEPROM, I2C, 16 Kbit, 2K x 8bit, 400 kHz, 8 Pins, NSOIC The devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as as 2048x8 bits, 1024x8 bits, 512x8 bits, 256x8 bits (M24C16, M24C08, M24C04 and M24C02).The devices are compatible with all I²C modes up to 400 kHz and can operate with a s Packaging: TRSupplier Type: Authorized Distributor75,000
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M24C32-WMN6P Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics STMicroelectronics The M24C32 is a 32-Kbit I²C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 4 K × 8 bits.This I²C EEPROM can operate with a supply voltage from 2.5 V up to 5.5 V over an ambient temperature range of -40 °C / 125 °C.The device is compliant with the Automotive standard AEC-Q100 grade 1. Packaging: BLKSupplier Type: Authorized Distributor6,739 Qty Price 1 0.372 10 0.3633 100 0.2964 500 0.2889 1,000 0.2802
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M24C32-WMN6TP Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics STMicroelectronics EEPROM, I2C, Serial, 32 Kbit, 4K x 8bit, 1 MHz, 8 Pins, SOIC N M24C32-WMN6TP is a 32Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 4K x 8 bits. Packaging: TRSupplier Type: Authorized Distributor90,499
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M24C08-WMN6TP Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics STMicroelectronics EEPROM Serial-I2C 8K-bit 1K x 8 3.3V/5V 8-Pin SO N T/R Packaging: N/ASupplier Type: Authorized Distributor75,000 Qty Price 7,500 0.1504 10,000 0.1443 15,000 0.1428 25,000 0.1415
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M24C08-WMN6P Category: EEPROM , Memory & Storage › Memory ICs STMicroelectronics STMicroelectronics EEPROM, I2C, Serial, 8 Kbit, 1K x 8bit, 400 kHz, 8 Pins, SOIC N The devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as as 2048x8 bits, 1024x8 bits, 512x8 bits, 256x8 bits (M24C16, M24C08, M24C04 and M24C02).The devices are compatible with all I²C modes up to 400 kHz and can operate with a s Packaging: RALSupplier Type: Authorized Distributor28,000
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ATSHA204A-STUCZ-T Category: EEPROM , Memory & Storage › Memory ICs Microchip Microchip The Microchip ATSHA204A is a full turnkey security device. It includes a 4.5Kb EEPROM divided into 16 slots. This array can be used for storage of keys, miscellaneous read/write, read-only, password or secret data, and consumption tracking. Access to the various sections of memory can be restricted in a variety of ways and then the configuration locked to prevent changes.Access to the chip is through a standard I²C interface at speeds up to 1Mb/sec. The chip also supports a single-wire interface that can reduce the number of GPIOs required on the system processor and/or reduce the number of pins on connectors. It is compatible with most UART or serial I/O controllers. System integration is eased with a wide supply voltage range and an ultra-low sleep current of less than 100nA. Packaging: TAPSupplier Type: Authorized Distributor4,481 Qty Price 1 0.873 25 0.7837 50 0.7713 100 0.7589
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KSZ8795CLXIC Category: Computing › Computing & Storage › Ethernet Switch , Memory & Storage Microchip Microchip The KSZ8795 is a highly-integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and RMII modes. The KSZ8795CLX product is built upon Microchip's industry-leading Ethernet latest analog and digital technology, with features designed to offload host processing and streamline your overall design. - Four integrated 10/100Base-T/TX MAC/PHYs - One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces - Small 80-pin LQFP package. Packaging: BLKSupplier Type: Authorized Distributor700 Qty Price 1 9.0396 10 8.2832 25 7.5268 50 7.4028 100 7.2788
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24AA01T-I/OT Category: EEPROM , Memory & Storage › Memory ICs Microchip Microchip The Microchip Technology Inc. 24AA01/24LC01B is a 1Kb Serial EEPROM. The device is organized as one block of 128 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V with standby and active currents of only 1 µA and 1 mA, respectively. The 24XX01 also has a page write capability for up to 8 bytes of data. The 24XX01 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN and MSOP packages, and is also available in the 5-lead SOT-23 package. Packaging: TRSupplier Type: Authorized Distributor114,000
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MT41K64M16TW-107:J Category: DRAM , Memory & Storage › Memory ICs Micron Micron DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Packaging: TRYSupplier Type: Authorized Distributor2,853 Qty Price 1 3.8657 10 3.7591 30 3.6524 50 3.5724 100 3.4658 250 3.3592 500 3.2525
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MT41K64M16TW-107:J TR Category: DRAM , Memory & Storage › Memory ICs Micron Micron DRAM Chip DDR3 SDRAM 1Gbit 64Mx16 1.35V 96-Pin FBGA T/R Packaging: N/ASupplier Type: Authorized Distributor2,000
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MT25QL128ABA8ESF-0SIT Category: Flash Memory , Memory & Storage › Memory ICs Micron Micron MT25QL128ABA8ESF-0SIT is a 3V, multiple I/O, sector erase, serial NOR flash memory. It is a high-performance multiple input/output serial flash memory device. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual, and quad input/output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. Packaging: TRYSupplier Type: Authorized Distributor3,454 Qty Price 1 3.4522 10 3.3569 30 3.2617 50 3.1903 100 3.095 250 2.9998 500 2.9046
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MT25QL128ABA8ESF-0SIT TR Category: Flash Memory , Memory & Storage › Memory ICs Micron Micron NOR Flash Serial (SPI, Dual SPI, Quad SPI) 3V/3.3V 128M-bit 128M/64M/32M x 1/2-bit/4-bit 6ns 16-Pin SOP-II T/R Packaging: N/ASupplier Type: Authorized Distributor5
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MT47H128M8SH-25E IT:M Category: DRAM , Memory & Storage › Memory ICs Micron Micron The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. Packaging: TRYSupplier Type: Authorized Distributor1,857 Qty Price 1 4.0635 10 3.9514 30 3.8393 50 3.7552 100 3.6431 250 3.531 500 3.4189
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MT25QL128ABA1ESE-0SIT Category: Flash Memory , Memory & Storage › Memory ICs Micron Micron The MT25Q is a high-performance multiple input/output serial Flash memory device manufactured on 45nm NOR technology. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual and quad input/ output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. Packaging: BLKSupplier Type: Authorized Distributor1,473 Qty Price 1 4.8112 10 4.03 25 3.9928 50 3.9432 100 3.906
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MT25QL128ABA1ESE-0SIT TR Category: Flash Memory , Memory & Storage › Memory ICs Micron Micron NOR Flash Serial (SPI, Dual SPI, Quad SPI) 3V/3.3V 128M-bit 128M/64M/32M x 1/2-bit/4-bit 6ns 8-Pin SOIC W T/R Packaging: N/ASupplier Type: Authorized Distributor12,000
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MT47H128M16RT-25EIT:C Category: DRAM Micron Micron N/APackaging: TRYSupplier Type: Authorized Distributor 1,440 Qty Price 1 14.5458 10 14.1446 30 13.7433 50 13.4423 100 13.0411 250 12.6398 500 12.2386
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MT47H128M16RT-25E AIT:C TR Category: DRAM , Memory & Storage › Memory ICs Micron Micron N/APackaging: TRSupplier Type: Authorized Distributor 1,000 Qty Price 1,000 15.6711 2,000 15.4504 4,000 15.009 6,000 14.6779 8,000 14.1261 10,000 13.9054 100,000 13.6846
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MT47H128M16RT-25E AIT:C Category: DRAM , Memory & Storage › Memory ICs Micron Micron N/APackaging: TRYSupplier Type: Authorized Distributor 1,260 Qty Price 1,260 15.6711 1,300 15.4504 2,600 15.009 6,300 14.6779 13,000 14.1261 63,000 13.9054 130,000 13.6846
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93LC86CT-I/SN Category: EEPROM , Memory & Storage › Memory ICs Microchip Microchip EEPROM Serial-Microwire 16K-bit 2K x 8/1K x 16 3.3V/5V 8-Pin SOIC N T/R Packaging: N/ASupplier Type: Authorized Distributor3,300
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